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TDA9203A
I2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER
. . . . . . . . . . .
70MHz TYPICAL BANDWIDTH AT 4VPP OUTPUT WITH 12pF CAPACITIVE LOAD 5.5ns TYPICAL RISE/FALL TIME AT 4VPP OUTPUT WITH 12pF CAPACITIVE LOAD POWERFULL OUTPUT DRIVE CAPABILITY BRT, CONT, DRIVE, OUTPUT DC LEVEL, OSD CONTRAST, BACK-PORCH CLAMPING PULSE WIDTH ARE I2C BUS CONTROLLED INTERNAL BACK-PORCH CLAMPING PULSE GENERATOR OSD WHITE BALANCE TRACKING INTERNAL OSD SWITCHES BLANKING AND FAST-BLANKING INPUTS VERY LARGE DRIVE ADJUSTMENT RANGE (48dB) SEMI-TRANSPARENT BACKGROUND ON OSD PICTURE ABL CONTROL
SHRINK 24 (Plastic Package) ORDER CODE : TDA9203A
PIN CONNECTIONS
DESCRIPTION The TDA9203A is a digitaly controlled wideband video preamplifier intended for use in mid range color monitor. All controls and adjustments are digitaly performed thanks to I2C serial bus. Contrast, brightness and DC output level of RGB signals are common to the 3 channels and drive adjustment is separate for each channel.Three I2C gain controlled OSD inputs can be switched with RGB signals using fast blanking command. Clamping of RGB signals is performed thanks to a flexible integrated system. The white balance adjustment is effective on brightness, video and OSD signals. The TDA9203A works for application using AC or DC coupled CRT driver. The ABL input provides a 12dB Max. attenuation on the current contrast value according average beam limitation voltage. Because of its features and due to component saving the TDA9203A leads to a very performant and cost effective application.
June 1998
IN1 OSD1 AVDD IN2 OSD2 AGND IN3 OSD3 ABL LGND SDA SCL
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
HSYNC PVCC1 OUT1 PGND1 PVCC2 OUT2 PGND2 PVCC3 OUT3 PGND3 BLK FBLK
9203A-01.EPS
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TDA9203A
PIN DESCRIPTION
Name IN1 OSD1 AVDD IN2 OSD2 AGND IN3 OSD3 ABL LGND SDA SCL Pin 1 2 3 4 5 6 7 8 9 10 11 12 Type I I I I I I/O I I I I/O I/O I Function 1st Channel Main Picture Input 1st Channel OSD Input 12V Analog VDD 2
nd
Name FBLK BLK PGND3 OUT3 PVCC3 PGND2 OUT2 PVCC2 PGND1 OUT1 PVCC1 HSYNC
Pin 13 14 15 16 17 18 19 20 21 22 23 24
Type I I I/O O I I/O O I I/O O I I
Function Fast Blanking Input Blanking Input 3rd Channel Power Ground 3rd Channel Output 3rd Channel Power VCC 2nd Channel Power Ground 2 2
nd nd
Channel Main Picture Input
2nd Channel OSD Input Analog Ground 3 Channel Main Picture Input 3 Channel OSD Input ABL Input Logic Ground Serial Data Line Serial Clock Line
rd rd
Channel Output Channel Power VCC
1st Channel Power Ground 1st Channel Power VCC Horizontal Synch Input
9203A-01.TBL 9203A-02.EPS
1st Channel Output
BLOCK DIAGRAM
BLK
14
FBLK
13
PVCC1
23
CLAMP VREF
3 1
BRIGHTNESS DRIVE
BPCP
CONTRAST
AVDD IN1 AGND
OUTPUT STAGE
22 OUT1 21 PGND1
6
8 bits IN2
4
20 PVCC2 19 OUT2 18 PGND2
BLUE CHANNEL
IN3 ABL
7 9
GREEN CHANNEL
16 OUT3 17 PVCC3
LGND 10
BPCP
15 PGND3
LATCHES I2C D/A BUS DECODER
OSD CONT IC VREF
2
OUTPUT DC LEVEL ADJUST
TDA9203A
24 11 12 2 5 8
HSYNC
SDA
SCL
OSD1
OSD2
OSD3
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TDA9203A
FUNCTIONAL DESCRIPTION Input Stage The R, G and B signals must be fed to the three inputs through coupling capacitors (100nF). The maximum input peak-to-peak video amplitude is 1V. The input stage includes a clamping function. This clamp is using the input serial capacitor as "memory capacitor" and is gated by an internally generated "Back-Porch-Clamping-Pulse (BPCP)". The synchronization edge of the BPCP is selected according bit 0 of register R8. When B0R8 is set to 1, the BPCP is synchronized on the leadingedgeof the blankingpulse BLKinputs on Pin14 (seeFigure1). B7R8 allowsto usepositive or negative blanking signal on Pin 14. At power on reset TDA9203Ause only positive blanking. Figure 1
BLK HSYNC
R,G,B video signals according to beam intensity. The operating range is 2.5V typicaly, from 5.3V to 2.8V. A typical 12dB Max. attenuationis applied to the signal whatever the current gain is. Refer to Figure 3 for ABL input attenuation range. In case of software control, the ABL input must be pulled to AVDD through a resistor to limit power consumption (see Figure 11). ABL input voltage must not exceeed AVDD. Input resistor is 10k and equivalent schematic given in Figure 11. Figure 3
2 0 -2 -4 -6 -8
9203A-03.EPS
Attenuation (dB)
BPCP
-10 -12 -14 1 2 3 4 5 6 7 VIN (V) 8 9
9203A-0X.EPS
Internal pulse width is controlled by I2C
When B0R8 is clear to 0, the BPCP is synchronized on the second edge of the horizontal pulse HSYNC inputs on Pin 24. An automatic function allows to use positive or negative horizontal pulse on Pin 24 (see Figure 2). Figure 2
HSYNC
BPCP
9203A-04.EPS
Brightness Adjustment (8 bits) As for the contrast adjustment, the brightness is controlled by I2C. The brightness function consists to add the same DC offset to the three R, G, B signals after contrast amplification. This DC-Offset is present only outside the blanking pulse (see Figure 4). The DC output level during the blanking pulse, is forced to "INFRA-BLACK" level (VDC). Drive Adjustment (3 x 8 bits) In order to adjust the white balance, the TDA9203A offers the possibility to adjust separatelythe overall gain of each complete video channel. The gain of each channel is controlled by I2C (8bits each). The very large drive adjustment range(48dB) allows different standard or custom color temperature. It can also be used to adjust the output voltages at the optimum amplitude to drive the C.R.T drivers, keepingthe whole contrast control for end-useronly. The drive adjustment is located after the CONTRAST, BRIGHTNESS and OSD switch blocks, so that the white balance will remains correct when BRT is adjusted, and will also be correct on OSD portion of the signal.
Internal pulse width is controlled by I2C
In both case BPCP width is adjustable by I2C, B1 and B2 of register R8 (see R8 Table P8). Contrast Adjustment (8 bits) The contrast adjustment is made by controlling simultaneously the gain of three internal variable gain amplifiers through the I2C bus interface. The contrast adjustment allows to cover a typical range of 48dB. ABL Control The TDA9203A I2C preamplifier provides an ABL input (automatic beam limitation) to attenuate
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TDA9203A
FUNCTIONAL DESCRIPTION (continued) OSD Inputs The TDA9203A includes all the circuitry necessary to mix OSDsignals intothe RGB main-picture. Four pins are dedicated to this function as follow. Three TTL RGB On Screen Display inputs (Pin 2, 5 and 8). These three inputs are connected to the three outputs of the corresponding ON-SCREENDISPLAY processor (ex : STV942x). One Fast Blanking Input (FBLK, Pin 13) which is also connected to the FBLK output of the same ON-SCREEN-DISPLAY processor. When a high level is present on FBLK, the IC will acts as follow : - The three main picture RGB input signals are internally switched to the internal input clamp reference voltage. - The three output signals are set to voltages correspondingto the state (0 or 1) on the three OSD inputs (see Figure 4). Example : If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1 respectively. Then OUT1, OUT2, OUT3 will be equal to VOSD, VBRT, VOSD, where : VBRT = VBLACK + BRT, VOSD = VBRT + OSD BRT is the brightness DC level I2C adjustable. OSD is the On-Screen Display signal value I2C adjustable from 0V to 5.5VPP by step of 0.36V. Semi-transparent function is controlled thanks to Bit 6 of R8 register (see Table 1). When semi-transparent mode is activated, video signal is divided by 2 (CONT). Table 1
FBLK OSD1 OSD2 OSD3 B6R8 0 1 0 1 1 1 1 x x x 0 x x 1 x x x x 1 x 0 x x x x x 0 1 0 0 1 1 1 1 1 Output Signal (OUTn) Video OSD (1) Video OSD OSD OSD Semi-transparent (2)
Output Stage The three output stagesincorporate threefunctions which are : - The blanking stage : When high level is applied to the BLK input (Pin 14), the three outputs are switched to a voltage which is 400mV lower than the BLACK level. The black level is the output voltage with minimum brightness when input signal video amplitude is equal to "0". - The output stage itself : It is a large bandwidth output amplifier which allow to deliver up to 5VPP on the three outputs (for 0.7V video signal on the inputs). - The output CLAMP : The IC also incorporates three internal output clamp (sample and hold system) which allow to DC shift the three output signals. The DC output voltage is adjustable through I2C with 4 bits. Practicaly, the DC output level allow to adjust the BLK level (VDC = 400mV under VBLACK) from 0.9V to 2.9V with 12 x 165mV. The overall waveforms of the output signal according to the different adjustment are shown in Figures 4 and 5. Serial Interface The 2-wires serial interface is an I2C interface. The slave address of the TDA9203A is DC (in hexadecimal).
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W 0
Data Transfer
The host MCU can write data into the TDA9203A registers. Read mode is not available. To write data into the TDA9203A, after a start, the MCU must send (see Figure 6) : - The I2C addressslave byte with a low level for the R/W bit. - The byte of the internal register address where the MCU wants to write data(s). - The data. All bytes are sent MSB bit first and the write data transter is closed by a stop.
Notes : 1. All OSD colors are displayed. 2. One OSD color is displayed as semi-transparent video without effect on brightness and DC level adjustment.
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TDA9203A
FUNCTIONAL DESCRIPTION (continued) Figure 4 : Waveforms VOUT, BRT, CONT, OSD
HSYNC BPCP BLK Video IN FBLK OSD IN
VOUT1, VOUT2, VOUT3 VCONT (4) VOSD (5) VBRT (3) VBLACK (2) VDC (1)
Notes : 1. 2. 3. 4. 5.
OSD
CONT BRT 0.4V fixed
Figure 5 : Waveforms (DRIVE adjustment)
HSYNC BPCP BLK Video IN FBLK OSD IN VOUT1, VOUT2, VOUT3 VCONT VOSD VBRT V BLACK V DC Two exemples of drive adjustment (1)
Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT and VOSD. Drive adjustment do not modify the following voltages : V DC and VBLACK.
Figure 6 : I2C Write Operation
SCL SDA Start I C Slave Address
2
W ACK
A7
A6
A5
A4
A3
A2
A1
A0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK Stop
Register Address
Data Byte
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9203A-08.EPS
9203A-07.EPS
9203A-06.EPS
VDC = 0.5 to 2.5V VBLACK = VDC + 0.4V VBRT = VBLACK + BRT (with BRT = 0 to 2.5V) VCONT = VBRT + CONT with CONT = k x Video IN (CONT = 5VP P max. for VIN = 0.7VPP) VOSD = VBRT + OSD with OSD = k1 x OSDIN (OSD max. = 5.5VPP, OSD min. = 360mVPP)
TDA9203A
QUICK REFERENCE DATA
Symbol Parameter Signal Bandwidth (4V PP/12pF load) Rise and Fall Time (4VPP/12pF load) Drive Adjustment Range on the 3 Channels separately Maximum Output Voltage (VIN = 0.7 VPP) Output Voltage Range (AC + DC) Min. Typ. 70 5.5 48 5 8 Max. Unit MHz ns VPP V
9203A-02.TBL 9203A-05.TBL 9203A-04.TBL 9203A-03.TBL
dB
ABSOLUTE MAXIMUM RATINGS
Symbol VS VIN1 VIN2 VIN3 VESD Tstg Tj Top er Parameter Supply Voltage (Pins 3-9-17-20-23) Voltage at any Input Pins (except SDA & SCL & Logical Inputs) Voltage at Input Pins SDA & SCL Voltage at Logical Inputs (OSD, FBLK, BLK, HSYNC) ESD Susceptability (Human body model ; 100pF Discharge through 1.5k) Storage Temperature Junction Temperature Operating Temperature Value 14 GND < VIN1 < VS GND < VIN2 < 5.5 GND < VIN3 < 5.5 2 - 40, + 150 150 0, + 70 Unit V V V V kV C C C
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Value 69 Unit
o
C/W
DC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Symbol VS IS VI VO VIL VIH IIN Supply Voltage Supply Current (All VS Pin current) Video Input Voltage Amplitude Typical Output Voltage Range Low Level Input (OSD, FBLK, BLK, HSYNC) High Level Input (OSD, FBLK, BLK, HSYNC) Input Current (OSD, FBLK, BLK, HSYNC) Parameter Test Conditions Pins 3-9-17-20-23 RL = 1k Pins 1-4-7 Pins 16-19-22 Pins 2-5-8-13-14-24 Pins 2-5-8-13-14-24 0.4V < VIN < 4.5V 2.4 -10 +10 0.5 Min. 10.8 Typ. 12 60 0.7 1 8 0.8 Max. 13.2 Unit V mA VPP V V V A
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TDA9203A
AC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, CL = 12pF, RL = 1k , unless otherwise specified)
Symbol AV CAR DAR GM Parameter Maximum Gain (20 log x VOUT AC/VIN AC) Contrast Attenuation Range Drive Attenuation Range Gain Match VOUT = 2.5VPP, VIN = 0.7VPP Contrast = Drive = Maxi x 0.7 (power-on reset value) At -3dB, VIN = 0.7VPP, VOUT = 4VPP Contrast = Drive = Maxi x 0.87 f = 1MHz, VOUT = 1VPP, VIN = 1VPP VIN = 0.7VPP, VOUT = 4VPP Contrast = Drive = Maxi x 0.87 Test Conditions Contrast & Drive at maximum VIN = 0.7VPP, Contrast & Drive at POR Min. Typ. 18 48 48 0.1 Max. Unit dB dB dB dB
BW DIS tR , tF BRT BRTM OSD CAR DC RL CT
Bandwidth Large Signal Video Output Distorsion (see Note) Video Output Rise and Fall Time (see Note) Brightness Maximum DC Level Brightness Minimum DC Level Brightness Matching Contrast Attenuation Range for OSD Input Output Maximum DC Level Output Minimum DC Level Equivalent Load on Video Output Croostalk between Video Channels (see Note)
70 0.3 5.5 2.5 0
MHz % ns V V mV dB V V k dB
BRT = 50%, Drive at POR
20 24 2.5 0.5
with Tj Tj Max. VOUT = 2.5VPP, VIN = 0.7VPP Contrast = Drive = Maxi x 0.7 (power-on reset value) fIN = 1MHz VABL = 5.3V Typical VABL = 2.8V Typical VABL = 5.3V See Figure 11 44
1
GABL IABL R ABL
ABL Input Current ABL Input Resistor
20 10
A k
Note : These parameters are not tested on each unit. They are measured during an internal qualification procedure which includes characterization on batches coming from corners of our processes and also from temperature characterization.
I2C ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Symbol VIL V IH IIN fSCL(Max.) VOL Parameter Low Level Input Voltage High Level Input Voltage Input Current (Pins SDA, SCL) SCL Maximum Clock Frequency Low Level Output Voltage SDA Pin when ACK Sink Current = 6mA 0.4V < VIN < 4.5V Test Conditions On Pins SDA, SCL 3 -10 200 0.6 +10 Min. Typ. Max. 1.5 Unit V V A kHz V
9203A-08.TBL
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9203A-06.TBL
ABL Min. Attenuation ABL Max. Attenuation
0 12
dB dB
TDA9203A
I2C INTERFACE TIMINGS REQUIREMENTS (see Figure 7)
Symbol tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tR, tF Parameter Time the bus must be free between 2 access Hold Time for Start Condition Set-up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set-up Time Data Rise and Fall Time of both SDA and SCL Min. 1300 600 600 1300 600 300 250 20 300 Typ. Max. Unit ns ns ns ns ns ns ns
9203A-09.TBL 9203A-09.EPS
ns
Figure 7
tBUF
SDA
tHDAT
tHDS
SCL
tSUDAT
tSUP
tHIGH
tLOW
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TDA9203A
REGISTER DESCRIPTION Registers Sub-address
Address (Hex) 01 02 03 04 05 06 07 08 Register Names Contrast Brightness Drive 1 Drive 2 Drive 3 Output DC Level OSD Contrast BP and Miscellaneous Function DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC 4-bit See R8 Table POR Value B4 B4 B4 B4 B4 08 08 04
Contrast Register (R1) (Video IN = 0.5VPP, Brightness at minimum,Drive at maximum)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 CONT (VPP) 0 0.015 0.031 0.062 0.125 0.25 0.5 1 2 2.812 4 G (dB) -30 -24 -18 -12 -6 0 6 12 15 18 X POR Value
Brightness Register (R2) (Drive at maximum)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 BRT (V) 0 0.010 0.020 0.040 0.080 0.160 0.320 0.640 1.28 1.8 2.56 X POR Value
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TDA9203A
REGISTER DESCRIPTION (continued) Drive Registers (R3, R4, R5) (Video IN = 0.5VPP, Brightness at minimum, Contrast at maximum)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 CONT (VPP) 0 0.015 0.031 0.062 0.125 0.25 0.5 1 2 2.812 4 G (dB) -30 -24 -18 -12 -6 0 6 12 15 18 X POR Value
Output DC Level Register (R6)
Hex 03 04 08 0F b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 1 b2 0 1 0 1 b1 1 0 0 1 b0 1 0 0 1 DC (V) 0.52 0.69 1.35 2.5 X POR Value
Code 00Hex, 01Hex and 02Hex : not to be used
OSD Contrast Register (R7) (VOSD IN = 2.4VMin.., Drive at maximum)
Hex 00 01 02 04 08 0F b7 0 0 0 0 0 0 b6 0 0 0 0 0 0 b5 0 0 0 0 0 0 b4 0 0 0 0 0 0 b3 0 0 0 0 1 1 b2 0 0 0 1 0 1 b1 0 0 1 0 0 1 b0 0 1 0 0 0 1 OSD (V) 0 0.36 0.73 1.46 2.93 5.5 G (dB) -24 -18 -12 -6 0 X POR Value
BP and Miscellaneous Register (R8)
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 Function BP Source = HSYNC BP Source = BLK BP Pulse Width = 0.33s BP Pulse Width = 0.66s BP Pulse Width = 1s BP Pulse Width = 1.3s Test Purposes Soft Blanking OFF Soft Blanking ON Semi Transparent OFF Semi Transparent ON Positive Blanking Polarity Selection Negative Blanking Polarity Selection X X X X X POR Value X
10/13
TDA9203A
INTERNAL SCHEMATICS Figure 8
AVDD IN
Figure 9
AVDD
P ins 1-4-7
OS D - BLK - FBLK P ins 2-5-8-13-14
AGND
9203A-10.EPS 9203A-11.EPS
AGND
AGND
AGND
Figure 10
AVDD 3 (20V)
Figure 11
AVDD Internal 5V
10k ABL
9203A-12.EPS
9
9203A-13.EPS
AGND
6
AGND
Figure 12
AVDD
Figure 13
LGND 10
S DA S CL P ins 11-12
(10V)
LGND AGND
9203A-14.EPS 9203A-15.EPS
AGND LGND
Figure 14
AVDD
Figure 15
PVCC P ins 17-20-23 AVDD
HSYNC 24
OUT Pins 16-19-22
AGND
9203A-16.EPS
AGND P GND P ins 15-18-21
LGND
11/13
9203A-17.EPS
TDA9203A
APPLICATION DIAGRAM
SYNCHRO EXTRACTOR BLK HSYNC VSYNC 1k 75 47 R GND R 75 47 G GND G 75 ABL GND 1k 100nF 100nF 100nF 1k 100nF 1k
1 2 3 4 5 6 7 8 9
+12V
47 B GND B
100nF IN1 OSD1 AVDD IN2 OSD2 AGND IN3 OSD3 ABL HSYNC 24 PVCC1 23 OUT1 22
T D A 9 2 0 3 A
100nF
BLUE OUT
PGND1 21 PVCC2 20 OUT2 19 PGND2 18 PVCC3 17 OUT3 16 PGND3 15 BLK 14 FBLK 13 100nF GREEN OUT 100nF RED OUT
10 LGND 11 SDA 12 SCL
GND
1k
GND
+5V
1 2 3
FBLK VSYNC HSYNC VDD PXCK CKOUT XTAL OUT XTAL IN
TEST 16
100nF
+5V
4 5 6
8MHz 33pF 33pF
7 8
S T V 9 4 2 6
G 14 R 13 GND 12 RESET 11 SDA 10 SCL
9
2.7k
B 15
100 SDA I2C BUS 10F 16V 22pF
9203A-18.EPS
SCL
12/13
TDA9203A
PACKAGE MECHANICAL DATA 24 PINS - PLASTIC DIP (SHRINK)
E E1
A1
A2
Stand-o ff B B1 e e1 e2
L c D E 24 13 F
.015 0,38 Gage Plane
A
1
12 e3
SDIP24
e2
Dimensions A A1 B B1 C D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86
Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240
Inches Typ.
Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270
3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62
0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30
2.54
3.30
0.10
0.130
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I 2C Patent. 2 Rights to use these components in a I C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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SDIP24.TBL
10.92 1.52 3.81
0.430 0.060 0.150
PMSDIP24.EPS

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